This invention relates to integrated circuits which include switching for high voltages, and particularly to programmable integrated circuits which include switching for a high programming voltage V.sub.PP.
In an integrated circuit, it is often necessary to use voltage levels that are higher than the nominal logic levels of the circuit. For example, in a normal memory circuit, the logic signals are typically 5-volt logic signals, but for programming it is necessary to have a high voltage V.sub.PP on the order of 12 volts.
However, a potential difference of 12V across a normal gate oxide can cause enough stress to degrade the oxide over the lifetime of the part and cause reliability problems. In order to protect against this degradation, it is necessary to reduce the voltage drop by distributing it over several transistors.
What is needed therefore is a circuitry which, upon a 5-volt logic control signal, will translate this signal into a 12-volt logic control signal and switch it over at output to a load circuit.
Such a circuit is shown in FIG. 1. In a standard way, it comprises two arms. Each arm has an N type switching transistor (M0, M1 respectively) and a P type controlled load transistor (M2, M3 respectively), series-connected between the ground and the high voltage V.sub.PP. The N type transistor of one arm is controlled at its gate by a switching signal C, and the N type transistor of the other arm is controlled at its gate by the complementary switching signal C . The P type transistor of each arm has its gate controlled by the connection point between the P type transistor and the N type transistor of the other arm.
In this way, in taking as an output one of the connection points between the P type transistor and the N type transistor of one of the arms, there is obtained, at output, a zero volt level or the level V.sub.PP, for example 12 volts. A circuit of this kind works as follows: when the switching signal C is at 5 volts, the N type transistor M0, which then has its gate potential at 5 volts and has its source connected to the ground, is on. The N type transistor M1, the gate potential of which, fixed by the complementary switching signal C , is then equal to 0 volts, is off. The transistor M0 therefore takes the potential of its drain towards 0 volts. The P type transistor M3, which is controlled at its gate by the drain of the transistor M0 and has its source connected to the high voltage V.sub.PP, is off. Since the transistor M1 is off, the connection point B between the transistors M3 and M1 tends towards 12 volts. The P type transistor M2, which therefore receives a voltage close to 12 volts at its gate, is off. A state of equilibrium is then set up. The transistors M1 and M2 being off, the potential of the drain of the transistor M0 gets stabilized at 0 volt and the potential of the drain of the transistor M3 gets stabilized at V.sub.PP.
When the switching signal C passes to 0 volts, the roles are reversed. At equilibrium, the connection point A between the transistors M0 and M2 will be at 12 volts and the connection point B between the transistors M1 and M3 will be at 0 volts.
With a circuit such as this, the drops in gate/drain, gate/source or drain/source voltage are very great. They are equal to the high voltage V.sub.PP. The transistors are subjected to a stress which may prompt the deterioration of their gate oxide by an aging phenomenon, punchthrough between the drain and the source or the breakdown of the drain/substrate or well junctions and the source/substrate or well junctions. These phenomena are well known.
Since the stress undergone by transistors constitutes a major drawback, a standard system of protection used is that of a protective cascade mounting of the P type load transistors and another protective cascade mounting of the N type switching transistors as is shown in FIG. 2. In each arm, a P type protection transistor M6, M7 and an N type protection transistor M4, M5 are series-connected between the P type transistor M2, M3 and the N type transistor M0, M1 of the switching circuit. Their gates are connected to the nominal supply voltage V.sub.CC of the circuit: the N type protection transistors M4, M5 are thus cascade-connected to protect the N type switching transistors M0, M1 and the P type protection transistors are cascade-mounted to protect the P type load transistors M2, M3. These P type load transistors M2, M3 are each controlled at their gate by the connection point between the N type switching transistor and the P type protection transistor of the other arm. The output level OUT is taken between the P type transistor and the N type protection transistor of one of the arms. (In the example of FIG. 2, this is taken from between the transistors M5 and M7.)
The N type protection transistors M4 and M5, which have their gates at V.sub.CC, prevent their sources from rising above the level V.sub.CC -V.sub.TN, otherwise they would no longer be on. The potential of the drain of the N type switching transistors M0, M1 therefore cannot rise above V.sub.CC -V.sub.TN, i.e. typically 4 volts.
The P type protection transistors M6 and M7, which have their gates at V.sub.CC, prevent their sources from falling below V.sub.CC -V.sub.TP, otherwise they would no longer be on. The potential of the drain of the P type load transistors M2, M3 therefore cannot fall below V.sub.CC +V.sub.TP, i.e. typically 6 volts. Since the drain potential of one arm is applied to the gate of the P type load transistor of the other arm, the same is true of these gates.
Thus, depending on the level of the switching signal C, either 0 volt or V.sub.PP is switched to the output OUT, but the drop in gate/drain, gate/source or source/drain voltage of the different load and switching protection transistors is far below that of the above assembly (FIG. 1) since the drops in voltage are distributed among four transistors whereas they were initially distributed between only two transistors. In an assembly such as this, the two P type transistors of an arm are used for the switching of V.sub.PP while the two N type transistors of an arm are used for the switching of 0 volt.
Now, it is possible that the supply voltage V.sub.CC will not be applied during a certain period of time. Under these conditions, if the high voltage V.sub.PP is present, large voltage drops may occur at the terminals of the protection transistors of the cascade assemblies.
Indeed, if V.sub.CC =0, the P type protection transistors have 0 volts at their gates and may have V.sub.PP at their sources. They are then conductive and transmit V.sub.PP to their drains: the N type protection transistors then have V.sub.PP at their drains while their gates are at 0 volts. The P type and N type protection transistors may therefore undergo major stress.
A new technique is therefore needed that will predictably prevent major stress to the P type and N type protection transistors. Such a means is provided herein.
The disclosed inventions solve this problem by using a different configuration. In the configuration of FIG. 2, the distribution of the voltage drops will make it possible, at equilibrium, to bring the voltage drops between gate and drain, gate and source or drain and source to 6 volts or less for normal levels of the voltages V.sub.PP and V.sub.CC.
According to the invention, it is proposed to enforce a small plus or minus voltage drop at the drains of the P type transistors and N type transistors of each of the arms. In this way, the voltage drop between gate and drain, gate and source and drain and source is reduced. A reduction by 1 volt reduces the electrical field to an extent sufficient to reduce the stress by several orders of magnitude.
According to the invention, it is proposed to place a forward biased diode in series between the P type transistor and the N type switching transistor of each of the arms. Since the diode is forward biased, it imposes a voltage drop that is equal to its threshold voltage. Thus, a voltage drop is added in each arm. For example, at the drain of the P type transistor of one of the arms, there will be a potential that is equal to the threshold voltage of the diode and no longer equal to 0 volt. At the drain of the N type transistor, there will be a potential V.sub.PP minus the threshold voltage of the diode. The protection device cannot be used to switch 0 volt or V.sub.PP to one and the same output. The effect of the drop in voltage due to the diode is passed on to one of the switched voltage levels.
According to an embodiment of the invention, the output OUT of the switching circuit is applied to the gate of a power transistor which will enable the application of the high voltage V.sub.PP to a load circuit.
According to another embodiment of the invention, the output OUT of the circuit is applied to the terminal of a resistor, the other terminal being connected to the high voltage. In this case, it is sought to switch the 0 volt and V.sub.PP levels to the output with very high precision.
According to the invention, then, it is proposed to interpose, between the resistor and the output OUT, an isolation transistor controlled at its gate by an output taken at the other arm of the switching circuit.
The output taken at the other arm between the P type transistor and the diode will enable the isolation transistor to be turned on or off and 0 volts or V.sub.PP to be applied to the terminals of the resistor.
According to another embodiment of the invention, a diode is placed between the output point, which controls the gate of the isolation transistor, and the P type transistor: the output which controls the gate is then between two diodes. The first diode increases the 0 volt level by the value of a threshold voltage, and the second diode reduces the V.sub.PP level by the value of a threshold voltage.
The invention therefore relates to a circuit for the switching of a high voltage V.sub.PP. This circuit comprises two arms, each having a P type transistor and an N type transistor series-connected between the high voltage V.sub.PP and the ground. The P type transistor is controlled at its gate by the connection point between the P type transistor and the N type transistor of the other arm. The N type transistor of one arm is controlled at its gate by a switching signal and the N type transistor of the other arm is controlled at its gate by the complementary switching signal.
A diode is connected between the P type transistor and the N type transistor in each of the arms.
In an application for the control of a high-voltage transfer transistor, the output of the switch-over circuit is taken between the diode and the P type transistor of one of the arms, to control the gate of the transfer transistor.
In an application for the switching of high voltage over to a resistive load according to the invention, an isolation transistor is placed between a resistor and an output of the circuit given by an arm, and this selection transistor is controlled at its gate by an output taken at the other arm.
Advantageously, a diode is placed on this other arm, between the first diode and the P type transistor. In this way, the selection transistor associated with the resistor is itself protected from stress.
Thus, the disclosed innovations provide the advantage of reduced stress on the gate oxide due to V.sub.PP switching. If gate oxide stress is within acceptable limits, this advantage can also be translated, in some integrated circuits, to permit use of thinner gate oxides.